A transistor sizing method for standard-cell optimization considering lithography effects
Jia-Syun Cai; Pin-Yuan Su; Chien-Lin Lee; Kuen-Yu Tsai
- Published
- Publisher
- SPIE
- Journal / collection
- DTCO and Computational Patterning III
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1117/12.3012028
The original publisher provides the full text and its access options.
Cite this source
Jia-Syun Cai; Pin-Yuan Su; Chien-Lin Lee; Kuen-Yu Tsai. A transistor sizing method for standard-cell optimization considering lithography effects. DTCO and Computational Patterning III. 2024-04-10. https://doi.org/10.1117/12.3012028