Low Power Cmos Adders Based on Alternative Structure Using Modified Double Pass Transistor Logic for High-Speed Arithmetic Applications
Sriram Sundar Subramanian; Mahendran Gandhi
- Published
- Publisher
- Elsevier BV
- Research area
- Semiconductors
- Source type
- Preprint / posted paper
- DOI
- 10.2139/ssrn.4783638
This is a preprint or other posted paper. Check the original source for its review and publication status.
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Cite this source
Sriram Sundar Subramanian; Mahendran Gandhi. Low Power Cmos Adders Based on Alternative Structure Using Modified Double Pass Transistor Logic for High-Speed Arithmetic Applications. Elsevier BV. 2024. https://doi.org/10.2139/ssrn.4783638