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An Efficient Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop using Single -Transistor-Clocked Buffer

Dr.p.Balamurali Krishna; Jallepalli Kalyani; Yelisetti ThirumalaVenkatesh; Vemasani Balaji; Tanneru Umamaheswari; Yajali Srivalli

Published
Publisher
Elsevier BV
Research area
Semiconductors
Source type
Preprint / posted paper
DOI
10.2139/ssrn.5048726

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Dr.p.Balamurali Krishna; Jallepalli Kalyani; Yelisetti ThirumalaVenkatesh; Vemasani Balaji; Tanneru Umamaheswari; Yajali Srivalli. An Efficient Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop using Single -Transistor-Clocked Buffer. Elsevier BV. 2025. https://doi.org/10.2139/ssrn.5048726

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