Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions
D. I. Cheremisinov; L. D. Cheremisinova
- Published
- Publisher
- United Institute of Informatics Problems of the National Academy of Sciences of Belarus
- Journal / collection
- Informatics
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.37661/1816-0301-2024-21-3-23-38
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Cite this source
D. I. Cheremisinov; L. D. Cheremisinova. Extraction of logical networks during decompiling transistor-level CMOS circuit descriptions. Informatics. 2024-09-30. https://doi.org/10.37661/1816-0301-2024-21-3-23-38