A Novel 2-Tier Stacked Vertical Channel GAA Transistor Architecture with Area-Saving 3-Dimensional Local Interconnect to Achieve Gb-Density 6T SRAM with Acceptable Low Standby Chip Leakage (~1mA)
Hang-Ting Lue; Weichen Chen; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 IEEE Silicon Nanoelectronics Workshop (SNW)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/snw63608.2024.10639203
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Cite this source
Hang-Ting Lue; Weichen Chen; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu. A Novel 2-Tier Stacked Vertical Channel GAA Transistor Architecture with Area-Saving 3-Dimensional Local Interconnect to Achieve Gb-Density 6T SRAM with Acceptable Low Standby Chip Leakage (~1mA). 2024 IEEE Silicon Nanoelectronics Workshop (SNW). 2024-06-15. https://doi.org/10.1109/snw63608.2024.10639203