Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor
Tong Zhang; Dingguo Zhang; Jing Jin; Patrick P. Mercier; Hui Wang
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 IEEE International Symposium on Circuits and Systems (ISCAS)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iscas58744.2024.10557912
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Cite this source
Tong Zhang; Dingguo Zhang; Jing Jin; Patrick P. Mercier; Hui Wang. Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor. 2024 IEEE International Symposium on Circuits and Systems (ISCAS). 2024-05-19. https://doi.org/10.1109/iscas58744.2024.10557912