A High-Density RRAM Memory Architecture With IO-Assisted-Core-Transistor 1T1R Array and Two-Level Encoding for Edge AI Models
Shengzhe Yan; Zhihang Qian; Xiangqu Fu; Zeyu Guo; Zhi Li; Jun Wang; Linfang Wang; Zhicheng Wu; Xiaoxin Xu; Chunmeng Dou; Feng Zhang; Bing Li; Jinshan Yue
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/tcad.2026.3660209
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Cite this source
Shengzhe Yan; Zhihang Qian; Xiangqu Fu; Zeyu Guo; Zhi Li; Jun Wang; Linfang Wang; Zhicheng Wu; Xiaoxin Xu; Chunmeng Dou; Feng Zhang; Bing Li; Jinshan Yue. A High-Density RRAM Memory Architecture With IO-Assisted-Core-Transistor 1T1R Array and Two-Level Encoding for Edge AI Models. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2026-10. https://doi.org/10.1109/tcad.2026.3660209