Optimal DfT test-transistor insertion for neural-network-classification-boosted latent pinhole detection and monitoring in Analog circuits
Sankhya Bhattacharya; Georges Gielen
- Published
- Publisher
- Elsevier BV
- Journal / collection
- AEU - International Journal of Electronics and Communications
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1016/j.aeue.2026.156416
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Cite this source
Sankhya Bhattacharya; Georges Gielen. Optimal DfT test-transistor insertion for neural-network-classification-boosted latent pinhole detection and monitoring in Analog circuits. AEU - International Journal of Electronics and Communications. 2026-10. https://doi.org/10.1016/j.aeue.2026.156416