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Research literature / Journal article

Design and Performance Analysis of Junctionless Vertically Stacked Gate All Around Transistor

R. Erigela; D. Vemana Chary; D. Venkatarami Reddy; B. Nageshwar Rao; B. Balaji; V. Agarwal; L. Singh

Published
Publisher
International Digital Organization for Scientific Information (IDOSI)
Journal / collection
International Journal of Engineering
Research area
Semiconductors
Source type
Journal article
DOI
10.5829/ije.2025.38.09c.07

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R. Erigela; D. Vemana Chary; D. Venkatarami Reddy; B. Nageshwar Rao; B. Balaji; V. Agarwal; L. Singh. Design and Performance Analysis of Junctionless Vertically Stacked Gate All Around Transistor. International Journal of Engineering. 2025. https://doi.org/10.5829/ije.2025.38.09c.07

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