Investigation of stability parameters of a gate-stack junctionless double-gate transistor (GS-JLDGT)-based 6T and 3T SRAM in the presence of traps
Neha Garg; Yogesh Pratap; Sneha Kabra
- Published
- Publisher
- Springer Science and Business Media LLC
- Journal / collection
- Journal of Computational Electronics
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1007/s10825-025-02285-7
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Cite this source
Neha Garg; Yogesh Pratap; Sneha Kabra. Investigation of stability parameters of a gate-stack junctionless double-gate transistor (GS-JLDGT)-based 6T and 3T SRAM in the presence of traps. Journal of Computational Electronics. 2025-02-25. https://doi.org/10.1007/s10825-025-02285-7