CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications
P. Nagarajan; N. Ashokkumar; Kavitha Thandapani; B. Manimaran; M. Krishnamurthy; P. Kabilamani
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/icpcsn62568.2024.00170
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Cite this source
P. Nagarajan; N. Ashokkumar; Kavitha Thandapani; B. Manimaran; M. Krishnamurthy; P. Kabilamani. CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications. 2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN). 2024-05-03. https://doi.org/10.1109/icpcsn62568.2024.00170