A Sige Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with SI Removal Process
KaiMin Feng; HaoYan Liu; HuaiZhi Luo; Xi Zhang; YongLiang Li
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Conference of Science and Technology of Integrated Circuits (CSTIC)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/cstic64481.2025.11017937
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Cite this source
KaiMin Feng; HaoYan Liu; HuaiZhi Luo; Xi Zhang; YongLiang Li. A Sige Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with SI Removal Process. 2025 Conference of Science and Technology of Integrated Circuits (CSTIC). 2025-03-24. https://doi.org/10.1109/cstic64481.2025.11017937