Compact 6T-SRAM Using Bottom-Gate Transistor in FD-SOI Process for Monolithic-3D Integration
Madhava Sarma Vemuri; Tanvir Ahmed; Umamaheswara Rao Tida
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/isvlsi61997.2024.00140
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Cite this source
Madhava Sarma Vemuri; Tanvir Ahmed; Umamaheswara Rao Tida. Compact 6T-SRAM Using Bottom-Gate Transistor in FD-SOI Process for Monolithic-3D Integration. 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2024-07-01. https://doi.org/10.1109/isvlsi61997.2024.00140