Design of T-Flip-Flop for Low Power Application Using CMOS D-Latch and Pass Transistor Logic (PTL)
Aditya Jagdale; Sanskruti Chavan; Shifa Ansari; Reshma Patil; Mrunalini Gavfale; Mamta Tikaria
- Published
- Publisher
- SCITEPRESS - Science and Technology Publications
- Journal / collection
- Proceedings of the 1st International Conference on Interdisciplinary Research in Science, Engineering, and Technology
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.5220/0014538400005061
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Cite this source
Aditya Jagdale; Sanskruti Chavan; Shifa Ansari; Reshma Patil; Mrunalini Gavfale; Mamta Tikaria. Design of T-Flip-Flop for Low Power Application Using CMOS D-Latch and Pass Transistor Logic (PTL). Proceedings of the 1st International Conference on Interdisciplinary Research in Science, Engineering, and Technology. 2025. https://doi.org/10.5220/0014538400005061