Transistor-Level Logic Gates Ranking Strategy for Selective Hardening
Glória D. Claro da Silva; Rafael B. Schvittz; Paulo F. Butzen
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 XIV Brazilian Symposium on Computing Systems Engineering (SBESC)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/sbesc65055.2024.10771816
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Cite this source
Glória D. Claro da Silva; Rafael B. Schvittz; Paulo F. Butzen. Transistor-Level Logic Gates Ranking Strategy for Selective Hardening. 2024 XIV Brazilian Symposium on Computing Systems Engineering (SBESC). 2024-11-26. https://doi.org/10.1109/sbesc65055.2024.10771816