Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F 2 DRAM Below Equivalent 10nm Node
Hang-Ting Lue; Wei-Chen Chen; Yu-Tang Lin; Keh-Chung Wang; Chih-Yuan Lu
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 IEEE International Memory Workshop (IMW)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/imw59701.2024.10536947
The original publisher provides the full text and its access options.
Cite this source
Hang-Ting Lue; Wei-Chen Chen; Yu-Tang Lin; Keh-Chung Wang; Chih-Yuan Lu. Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F 2 DRAM Below Equivalent 10nm Node. 2024 IEEE International Memory Workshop (IMW). 2024-05-12. https://doi.org/10.1109/imw59701.2024.10536947