CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing
Pengcheng Huang; Yaohua Wang; Zhenyu Zhao; Daheng Yue
- Published
- Publisher
- Institute of Electrical and Electronics Engineers (IEEE)
- Journal / collection
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.1109/tvlsi.2023.3328592
The original publisher provides the full text and its access options.
Cite this source
Pengcheng Huang; Yaohua Wang; Zhenyu Zhao; Daheng Yue. CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2024-01. https://doi.org/10.1109/tvlsi.2023.3328592