A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process
Soumika Majumder; Lean Karlo Santos Tolentino; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri; Mitch Ming-Chi Chou; Chua-Chin Wang
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 21st International SoC Design Conference (ISOCC)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/isocc62682.2024.10762163
The original publisher provides the full text and its access options.
Cite this source
Soumika Majumder; Lean Karlo Santos Tolentino; Oliver Lexter July Alvarez Jose; Venkata Naveen Kolakaluri; Mitch Ming-Chi Chou; Chua-Chin Wang. A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. 2024 21st International SoC Design Conference (ISOCC). 2024-08-19. https://doi.org/10.1109/isocc62682.2024.10762163