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Research literature / Conference paper

A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation

Zihan Yin; Annewsha Datta; Shwetha Vijayakumar; Ajey Jacob; Akhilesh Jaiswal

Published
Publisher
ACM
Journal / collection
Proceedings of the Great Lakes Symposium on VLSI 2024
Research area
Semiconductors
Source type
Conference paper
DOI
10.1145/3649476.3658789

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Zihan Yin; Annewsha Datta; Shwetha Vijayakumar; Ajey Jacob; Akhilesh Jaiswal. A 9 Transistor SRAM Featuring Array-level XOR Parallelism with Secure Data Toggling Operation. Proceedings of the Great Lakes Symposium on VLSI 2024. 2024-06-12. https://doi.org/10.1145/3649476.3658789

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