Low sheet resistance buried metal bit line realized by high-temperature metal CVD process in vertical channel transistor array
Chao Tian; Jiabao Sun; Yanlei Ping; Naizheng Wang; Baodong Han; Zhao Liu; Yongjie Li; Jingheng Meng; Hongbo Sun; Guilei Wang; Jian Chu; Guangsu Shao; Jie Shen; Yunsong Qiu; Ted Park; Deyuan Xiao; Abraham Yoo; Chao Zhao
- Published
- Publisher
- IOP Publishing
- Journal / collection
- Japanese Journal of Applied Physics
- Research area
- Semiconductors
- Source type
- Journal article
- DOI
- 10.35848/1347-4065/ad3833
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Chao Tian; Jiabao Sun; Yanlei Ping; Naizheng Wang; Baodong Han; Zhao Liu; Yongjie Li; Jingheng Meng; Hongbo Sun; Guilei Wang; Jian Chu; Guangsu Shao; Jie Shen; Yunsong Qiu; Ted Park; Deyuan Xiao; Abraham Yoo; Chao Zhao. Low sheet resistance buried metal bit line realized by high-temperature metal CVD process in vertical channel transistor array. Japanese Journal of Applied Physics. 2024-04-01. https://doi.org/10.35848/1347-4065/ad3833