Low Dark Noise and 8.5k e − Full Well Capacity in a 2-Layer Transistor Stacked 0.8μ m Dual Pixel CIS with Intermediate Poly-Si Wiring
Y. Satake; Y. Tanaka; S. Sato; M. Takase; M. Hoyano; S. Kasukawa; M. Tomita; Y. Kikuchi; J. Yamamoto; K. Tokuhiro; K. Furumoto; H. Sugino; Y. Murakawa; S. Yamazaki; H. Mizuno; H. Tomita; N. Yamada; T. Hirano; Y. Kitano
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 IEEE International Electron Devices Meeting (IEDM)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/iedm50854.2024.10873371
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Cite this source
Y. Satake; Y. Tanaka; S. Sato; M. Takase; M. Hoyano; S. Kasukawa; M. Tomita; Y. Kikuchi; J. Yamamoto; K. Tokuhiro; K. Furumoto; H. Sugino; Y. Murakawa; S. Yamazaki; H. Mizuno; H. Tomita; N. Yamada; T. Hirano; Y. Kitano. Low Dark Noise and 8.5k e − Full Well Capacity in a 2-Layer Transistor Stacked 0.8μ m Dual Pixel CIS with Intermediate Poly-Si Wiring. 2024 IEEE International Electron Devices Meeting (IEDM). 2024-12-07. https://doi.org/10.1109/iedm50854.2024.10873371