Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process
Shinichi Nishizawa; Shinji Kimura
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/vlsitsa60681.2024.10546399
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Cite this source
Shinichi Nishizawa; Shinji Kimura. Standard Cell Structure and Transistor Reordering for Mitigating Area Penalty in Double Diffusion Break FinFET Process. 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA). 2024-04-22. https://doi.org/10.1109/vlsitsa60681.2024.10546399