Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables
Subhadip Ghosh; Endalk Y. Gebru; Chandramouli V. Kashyap; Ramesh Harjani; Sachin S. Sapatnekar
- Published
- Publisher
- IEEE
- Journal / collection
- 2025 Design, Automation & Test in Europe Conference (DATE)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.23919/date64628.2025.10993030
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Cite this source
Subhadip Ghosh; Endalk Y. Gebru; Chandramouli V. Kashyap; Ramesh Harjani; Sachin S. Sapatnekar. Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. 2025 Design, Automation & Test in Europe Conference (DATE). 2025-03-31. https://doi.org/10.23919/date64628.2025.10993030