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Research literature / Conference paper

Exploiting HPC Techniques to Parallelise Simulation of 10B+ Transistor SoCs

Jonathan Balkind

Published
Publisher
IEEE
Journal / collection
2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)
Research area
Semiconductors
Source type
Conference paper
DOI
10.1109/vlsitsa60681.2024.10546385

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Jonathan Balkind. Exploiting HPC Techniques to Parallelise Simulation of 10B+ Transistor SoCs. 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA). 2024-04-22. https://doi.org/10.1109/vlsitsa60681.2024.10546385

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