VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur; Baleegh Ahmad; Hammond Pearce; Benjamin Tan; Brendan Dolan-Gavitt; Ramesh Karri; Siddharth Garg
- Published
- Publisher
- Association for Computing Machinery (ACM)
- Journal / collection
- ACM Transactions on Design Automation of Electronic Systems
- Research area
- AI & compute
- Source type
- Journal article
- DOI
- 10.1145/3643681
The original publisher provides the full text and its access options.
Cite this source
Shailja Thakur; Baleegh Ahmad; Hammond Pearce; Benjamin Tan; Brendan Dolan-Gavitt; Ramesh Karri; Siddharth Garg. VeriGen: A Large Language Model for Verilog Code Generation. ACM Transactions on Design Automation of Electronic Systems. 2024-04-22. https://doi.org/10.1145/3643681