Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application
Shriharsh Prasad Behera; Mahesh Vaidya; Alok Naugarhiya
- Published
- Publisher
- IEEE
- Journal / collection
- 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID)
- Research area
- Semiconductors
- Source type
- Conference paper
- DOI
- 10.1109/vlsid60093.2024.00005
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Cite this source
Shriharsh Prasad Behera; Mahesh Vaidya; Alok Naugarhiya. Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application. 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID). 2024-01-06. https://doi.org/10.1109/vlsid60093.2024.00005